1. Field of the Invention
The present invention relates to a power semiconductor device for use in handling high electric power, and more particularly, to a power semiconductor device comprising a vertical-type power MOSFET with a superjunction structure.
2. Description of the Related Art
In one type of the power semiconductor devices such as a vertical-type power MOSFET, the on-resistance thereof depends on the electric resistance of a conductive layer or the drift layer. The doped impurity concentration which determines the electric resistance of the drift layer depends on the breakdown voltage of the PN junction formed between the base layer and the drift layer, and so cannot be increased beyond a certain limit. In other words, there is a so-called trade-off relationship between the breakdown voltage and the on-resistance. To obtain a semiconductor device that wastes only a small amount of power, the trade-off must be improved. The improvement of the trade-off is limited by the material used in the device. To achieve a power semiconductor device having an on-resistance lower than that of a conventional device, it is necessary to improve the trade-off beyond the limit.
It is known that this problem can be overcome by a MOSFET having a RESURF structure or a superjunction structure, which is a structure in which p-type pillar layers and n-type pillar layers are repeatedly arranged, buried within the drift layer.
FIG. 15 is a schematic sectional view showing the structure of a vertical-type power MOSFET having a RESURF structure.
In the MOSFET, an n+ type drain layer (n+ substrate) 101 is formed on one surface of the n-type pillar layer 103. On the other surface of the n+ type drain layer 101, a drain electrode 105 is formed. In the other surface region of the n-type pillar layer 103, a plurality of p-type base layers 106 are selectively formed. In the surface region of each p-type base layer 106, n+ type source layers 107 are selectively formed. On the surface region of the n-type pillar layer 103 between two n+ type source layers 107 provided in adjacent two p-type base layers 106, a gate electrode 110 is formed via a gate insulating film 109.
In addition, a source electrode 108 is formed on the n+ type source layers 107 formed in each of the p-type base layers, so as to sandwich the gate electrode 110 between the source electrodes 108. In the n-type pillar layer 103 between the p-type base layer 106 and the drain layer 101, p-type pillars 104 in contact with the p-type base layers 106 are formed. In short, pn junctions formed between the n-type pillar layers 103 and the p-type pillars 104 are arranged alternately in the lateral direction throughout the entire drift layer. This is called a vertical-type RESURF structure or a so-called superjunction structure.
In a MOSFET having such a superjunction structure, the impurity concentration of the n-type pillar layer 103 can be increased by reducing the interval (cell width) between adjacent pillars 104, thereby reducing the on-resistance.
A process for burying the pillars 104 of the superjunction structure in the MOSFET will now be described more specifically. In an n-type layer formed on an Si substrate by the epitaxially growing method boron ions are selectively implanted into a surface portions of the n-type layer at which the pillars are being formed. The n-type layer is then allowed to grow epitaxially to bury the boron ions implanted into the n-type layer. Again, boron ions are selectively implanted into the same surface portions of the n-type layer grown epitaxially in the above step and the n-type layer is again allowed to grow epitaxially. As described, this process which is called as injection/epitaxial growth of boron-ion implantation and epitaxial growth is repeated a plurality of times, and the resultant structure is heat treated to diffuse the injected boron ions. In this way, the p-type pillars 104 extending in the vertical direction, as seen in the sectional view of FIG. 15, is formed.
However, a method of forming such a superjunction structure within the drift layer requires a complicated manufacturing process of repeating n-type layer epitaxial growth and p-type impurity implantation alternately. Because of this, the wafer manufacturing cost becomes higher than that of conventional power MOSFETs.
As described above, the on-resistance can be reduced by reducing the cell width or the interval of the pillars 104. However, to reduce the cell width, the depth and width of the boron ions implanted each time must be reduced and, instead, implantation/epitaxial growth must be repeated more. As a result, the wafer manufacturing cost increases.
The structure of a MOSFET having a superjunction structure is disclosed in, for example, National Patent Publication No. P2001-501042A.
A vertical-type power MOSFET having a conventional superjunction structure formed therein has the disadvantage that a complicated manufacturing process is required in order to reduce the cell width, that is, to reduce the on-resistance.